The 2009 International Conference on High Performance Computing and Simulation (HPCS 2009)
June 21 - 24, 2009, Leipzig, Germany

TUTORIAL V

Hardware-aware Computing on Multicore Processors and Accelerators

Rainer Buchty1, Jan-Philipp Weiß2

1Institute of Computer Science & Engineering, Chair for Computer Architecture
2Shared Research Group New Frontiers in High Performance Computing
Exploiting Multicore and Coprocessor Technology
Karlsruhe Institute of Technology
Germany

TUTORIAL DESCRIPTION
The paradigm shift towards multicore and coprocessor technologies is offering a great potential of computational power for scientific and industrial applications. In turn it is, however, posing considerable challenges to application-software development. Furthermore, heterogeneity of hardware platforms is growing at the processor level and by adding coprocessors and accelerators. At present, performance gains for compute-intensive applications can only be achieved by exploitation of coarse- and fine-grained parallelism on all system levels and improved scalability with respect to constantly increasing core counts. A key methodology is hardware-aware computing where in all production steps –  ranging from algorithm design and coding to software development and program handling – detailed knowledge of processor, memory, and network details is profitably utilized. Already today, a wide variety of new hardware concepts, different processing and programming models, as well as parallel languages and programming environments exist. In the near future, these technologies are expected to keep on diverging.

This tutorial aims at giving insights to emerging hardware technologies such as multi- and manycore processors, Graphics Processing Units, accelerator boards like ClearSpeed's solution, the Cell Broadband Engine, and Field Programmable Gate Arrays (FPGAs) in scientific and high-performance computing. In addition to architectural details we outline parallel programming aspects and elements of typical applications.

TUTORIAL OUTLINE
We cover the following topics:

TARGET AUDIENCE
The target audience includes graduate students, researchers, and practitioners who are interested in designated topics around multicore and accelerator techniques including hardware and programming aspects.

REQUIRED BACKGROUND
Interest in parallel programming, scientific computing and basic hardware knowledge.

TUTORIAL DURATION
The tutorial material will be presented in a 2 to 3-hour session.

A/V AND EQUIPMENT
Typical presentation facilities.

INSTRUCTOR BIOGRAPHY
RAINER BUCHTY
(buchty@kit.edu , http://ca.itec.uka.de/)
Rainer Buchty studied computer science at the Technische Universität München where he also earned his doctorate degree in 2002, working on programmable cryptographic architectures. This work led to an industrial consulting position at Agere Systems, USA, where, targeting next-generation network processors, he pursued his work on cryptographic building blocks resulting in a US patent granted in 2007. Since 2004, Dr. Buchty is a member of Prof. Wolfgang Karl's Chair for Computer Architecture at Universität Karlsruhe (TH) where his work concentrates on parallel, application-specific, and reconfigurable architectures including tools and programming models to harness the power of such future systems.
JAN-PHILIPP WEISS
(jan-philipp.weiss@kit.edu , http://srg-multicore.rz.uni-karlsruhe.de/ )
Jan-Philipp Weiss studied mathematics at the universities of Stuttgart and Freiburg and worked as a researcher at the universities of Kaiserslautern and Karlsruhe. He received a Ph.D. from Universität Karlsruhe (TH) in 2006 and was appointed junior professor in 2008. He is leading a Shared Research Group at Karlsruhe Institute of Technology (KIT) in joint collaboration with the company Hewlett-Packard. Work of this group addresses profitable deployment of emerging hardware platforms in scientific computing.